1. Technical Field
This disclosure relates to semiconductor devices and more particularly, to a fast delay locked loop with the capability of detecting multiple phase differences between a clock signal and a delayed clock signal.
2. Description of the Related Art
Conventional double data rate (DDR) synchronous dynamic random access memories (SDRAM) employ a plurality of delay locked loop circuits (DLL). These DLL circuits are employed to synchronize delay between two signals, for example, a clock signal and a delayed clock signal.
Referring to FIG. 1, a delay lock loop 10 is shown. A clock receiver 11 receivers clock signals (CK/ and its complement bGK). Conventional DLL implementations usually have one phase detector (PD) circuit 12 to detect the phase difference between a reference clock (Ref_clock) and a feedback clock (FB_clock) for clock synchronization. Based on the phase difference, an output of phase detector 12 is +, xe2x88x92 and 0 and controls a delay line (DL) control unit 14 to increment or decrement a delay line 16 by one delay unit (e.g., xcx9c50 to xcx9c100 ps depending on the design implementation). The increment/decrement of the DL line 16 is performed with every clock cycle or if a filter is implemented in the DL control unit 14, with every nth clock cycle.
If the Ref_clock and FB_clock are in phase the output of the PD 12 is 0 and the DLL 10 is locked. To maintain stable conditions while the DLL 10 is locked the PD 12 has a  greater than PD offset= or a  greater than timing dead zone= in the order of 1 times a delay unit or 2 times a delay unit.
Referring to FIG. 2, a timing relation of the FB_clock with the  greater than PD offset= of one delay unit and the number of  greater than + and xe2x88x92xe2x80x2 delay units to the reference Ref_clock is shown. The delay in FIG. 2 shows simple cases where a first FB_clock edge 20 can be approximately synchronized in 2 (+) delay units or a second FB_clock edge 22 can be approximately synchronized in 1 (xe2x88x92) delay unit. If a phase shift between the Ref_clock and FB_clock occurs due to noise and temperature variation on a chip the DLL needs a number, sometimes hundreds, of clock cycles to synchronize Ref_clock and FB_clock.
In DDR SDRAM=s DLL=s are required to synchronize the DQ (or output pin) to the system clock CK/bCK in a read operation. In a conventional DLL scheme, the DLL update is usually performed with every clock cycle and therefore requires all parts of the DLL to be active. As a result, in a power down mode, the DLL will be active and consume power. For power savings while in power down mode, the DLL can be automatically turned off and the state of the pointer settings (e.g., from the delay control unit) is xe2x80x9cfrozenxe2x80x9d. (Note: No DLL reset is performed in this operation).
Due to temperature and voltage variation on the chip, the pointer settings while entering the power down mode may not be accurate anymore after the power down mode exit. The temperature and voltage variation is usually caused by different modes of operations, e.g., read/write cycles, bank activate cycles or chip idle mode, and temperature and voltage variation affect the internal timing of the DLL and the pointer settings. Therefore, an immediate read cycle after power down mode exit may not be possible. Further, the synchronization of the system clock to the DQ=s (output pins of the chip) in a single read cycle may not be accurate, hence, compromising the necessary timing margins.
Therefore, a need exists for a delay lock loop (DLL) which provide greater margin is synchronizing signals, such that the signals are synchronized quickly and accurately to improve system performance.
A delay lock loop, in accordance with the present invention, includes a plurality of phase detectors each receiving a first clock signal and a second clock signal. Each phase detector includes a specified delay range for detecting phase differences between the first and second clock signals in that range. A delay line includes an input and an output. The first clock signal is received at the input, and the second clock signal includes a delayed first clock signal. An amount of delay is applied to the first clock signal, which is adjusted in the delay line in accordance with control signals of the phase detectors.
In alternate embodiments, the plurality of phase detectors may include five phase detectors. The specified ranges may include multiples of a delay unit. The delay lock loop may include a control unit coupled to the phase detectors for receiving the control signals and generating a delay line control signal which enables or disables delay elements in the delay line to adjust delay in the second clock signal. The delay lock loop may include an adjustment control circuit coupled to the phase detectors and the control unit, the adjustment control circuit being adapted to interpret the control signals from the phase detectors for the control unit to determine an adjustment size for a change in delay. The adjustment size may include at least two discrete sizes. The control signals may include one of an increment state, a decrement state and a lock state. The control signals of one of the phase detectors may be employed to determine when to increment, decrement or lock the delay of the second clock cycle. The phase detectors may include delay elements adapted to generate an internal clock signal to compare with one of the first clock signal and the second clock signal to determine a phase difference between the internal clock signal and one of the first clock signal and the second clock signal. The phase detector may output the control signal in accordance with the phase difference between the internal clock signal and one of the first clock signal and the second clock signal. Another delay lock loop in accordance with the present invention, includes a delay line including an input and an output. A first clock signal is received at the input, and a second clock signal includes a delayed first clock signal at the output. At least two phase detectors are provided. Each phase detector receives the first clock signal and the second clock signal. The phase detectors for determine a phase difference between the first clock signal and the second clock signal in a specified phase difference range and output a control signal in accordance with the phase difference. An adjustment circuit is coupled to outputs of the phase detectors for interpreting the control signals from the phase detectors. The adjustment circuit is adapted to determine whether to increment, decrement or lock the delay line and to determine a size of the increment or decrement to reduce the phase difference between the first and second clock signals.
In alternate embodiments, the at least two phase detectors may include five phase detectors. The specified phase difference ranges may include multiples of a delay unit. The adjustment circuit may provide a delay line control signal which enables or disables delay elements in the delay line to adjust delay in the second clock signal. The adjustment circuit may include an adjustment control circuit coupled to the phase detectors. The adjustment control circuit is adapted to interpret the control signals from the phase detectors for the control unit to determine an adjustment size for a change in delay. The adjustment size may include at least two discrete sizes. The control signals may include one of an increment state, a decrement state and a lock state. The control signals of one of the phase detectors is preferably employed to determine when to increment, decrement or lock the delay of the second clock cycle. The phase detectors may include delay elements adapted to generate an internal clock signal to compare with one of the first clock signal and the second clock signal to determine a phase difference between the internal clock signal and one of the first clock signal and the second clock signal. The phase detector may output the control signal in accordance with the phase difference between the internal clock signal and one of the first clock signal and the second clock signal.
A method for adjusting delay in a delay lock loop, in accordance with the present invention, includes the steps of providing a delay lock loop including a plurality of phase detectors, each receiving a first clock signal and a second clock signal. Each phase detector includes a specified delay range for detecting phase differences between the first and second clock signals in that range. A delay line includes an input and an output, and the first clock signal is received at the input and the second clock signal includes a delayed first clock signal. The method further includes the steps of determining phase differences for each phase detector, outputting control signals from the phase detectors, determining whether to increment, decrement or lock the delay lock loop, if an increment or decrement is determined, determining an amount of delay to be incremented or decremented by employing the control signals of all the phase detectors, and adjusting the delay line in accordance with the control signals. The method may further include the step of adjusting the delay of the second clock cycle by a plurality of delay units in a single clock cycle.
In other methods, the step of repeating the method steps until achieving a lock state is included. The specified phase difference ranges may include multiples of a delay unit. The amount of delay to be incremented or decremented may be adjusted by at least two discrete sizes. The control signals may include one of an increment state, a decrement state and a lock state. The control signals of one of the phase detectors is employed to determine when to increment, decrement or lock the delay of the second clock cycle.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.